1. Field of the Invention
The present invention relates to a method for manufacturing a semiconductor device, and more specifically, to a process for forming a planarized surface in a semiconductor device having a multilevel interconnection structure.
2. Description of Related Art
With advanced fine patterning in LSI (large scale integrated circuit) technology, pitches of interconnection conductors have also been reduced, and simultaneously, the number of interconnection conductor levels is also increased. Because of the increase of the number of interconnection conductor levels, a so-called altitude difference becomes large. Here, the altitude difference means the difference between a height from a silicon substrate surface to a top surface of an interlayer film in a region in which no interconnection conductor is formed, and a height from a silicon substrate surface to an top surface of an interlayer film in another region in which an interconnection conductor is formed. In the case of carrying out, on this interlayer film having undulations, a lithography, for example, a patterning of an upper level aluminum interconnection layer, or a formation of through holes, a profile of the interlayer film adversely influences a patterning limit of a deposited resist for the lithography.
Here, a patterning characteristics of the resist in a region having steps will be explained with reference to FIG. 1, which is a sectional view of a resist layer deposited on a step portion.
The case of coating a resist film on a surface having a difference in altitude (stepped surface) and patterning the coated resist film, is different in two points from the case of coating and patterning a resist film on a flat surface. The first difference is that the thickness of the resist film varies in the vicinity of the stepped portion. The second difference is that an optimum focal depth of a stepper is different between a high altitude region and a low altitude region. Here, the focal depth is not a distance between a lens of the stepper and a local resist surface, but is a distance between the lens and a wafer (substrate).
Generally, the profile of the resist pattern is determined by an exposed image, an exposure intensity and an intensity of a reflected light from an underlying layer.
In the high altitude region, the patterned resist profile is determined by the exposed image and the exposure intensity. Particularly, a positive photoresist in a region having the altitude higher than a focal depth margin (the tolerance of the focal depth capable of patterning with an acceptable precision), it is a problem that the patterned resist profile is thinned by a spreading of the exposed image. A change in the exposure intensity is substantially negligible. On the other hand, in a region in the vicinity of the step, it is a problem that resolution is lowered by an increased thickness of the resist film, and the patterned resist profile is determined by the exposure intensity and the intensity of the reflected light from the underlying layer. Accordingly, the patterned resist profile is determined by different factors in the high altitude region and in the low altitude region in the vicinity of the step, respectively.
Next, explanation is turned to a conventional interlayer film formation process and the patterning of a resist used in the conventional interlayer film formation process. The conventional interlayer film formation process can be divided broadly into a local planarization process utilizing a flatness of a deposited film, and a global planarization process utilizing a technique other than the deposited film.
The local planarization process is generally exemplified by a resist etch-back process utilizing a coated resist film, and a SOG (Spin On Glass) process. By using these interlayer film planarization processes, local variation in thickness of the resist film can be suppressed, and therefore, the lowering of the focal depth margin attributable to variation in thickness of the resist can be suppressed. As a result, the local planarization process has been utilized in semiconductor devices in which the focal depth does not become a problem even if the pitch of the interconnection conductors is reduced and/or the thickness of the interconnection conductors is increased.
Referring to FIG. 2, there is shown a graph illustrating the dependency of a device maximum altitude difference and a resist focal depth margin for patterning a third level interconnection metal layer, to a minimum design size (pattern size) in a three-level interconnection metal structure.
The smaller the minimum design size (pattern size) becomes, the thinner the resist becomes, for the purpose of making it possible to realize a finer resist patterning. As a result, from the viewpoint of an etching precision and an anti-etching property of the resist, the interconnection layer has to be thinned in the three-level interconnection metal structure. Accordingly, the device maximum altitude difference correspondingly becomes small.
However, if because of reduction of the minimum design size (pattern size) the focal depth margin lowers below the device maximum altitude difference, it becomes impossible to simultaneously pattern the resist in the high altitude region and the resist in the low altitude region. On the other hand, the resist is actually required to have a thickness of 2.0 .mu.m at minimum in order to ensure a thickness which can sufficiently proof against the etching of an interconnection conductor material. Accordingly, semiconductor devices having the minimum design size of not greater than 0.8 .mu.m, at which the focal depth margin becomes lower than the device maximum altitude difference as the result of the reduction of the minimum design size (pattern size), cannot be realized if the global planarization process is not utilized.
The global interlayer film planarization technology includes a CMP (chemical mechanical polishing) process (R. R. Uttecht et al., "A FOUR-LEVEL-METAL FULLY PLANARIZED INTERCONNECT TECHNOLOGY FOR DENSE HIGH PERFORMANCE LOGIC AND SRAM APPLICATIONS", IEEE VMIC Conf. (Jun. 11-12, 1991), pages 20-26, 1991), a selective oxide film growth utilizing a CVD (chemical vapor deposition) (T. Homma et al., "A NEW INTERLAYER FORMATION TECHNOLOGY FOR COMPLETELY PLANARIZED MULTILEVEL INTERCONNECTION BY USING LPD", 1990 Symp. on VLSI Tech., pages 3-4, 1990), and a block resist process utilizing an inverted pattern resist of the underlying interconnection pattern (A. Schlitz et al., "Two-Layer Planarization Process", J. Electrochem. Soc.: SOLID STATE SCIENCE AND TECHNOLOGY, pages 178-181, January 1986; and Japanese Patent Application Laid-open No. JP-A-60-245229).
In particular, the block resist process is widely utilized since the global planarization can be realized while introducing no new apparatus into a manufacturing line (S. Fujii et al., "A Planarization Technology Using a Bias-Deposited Dielectric Film and an Etch-Back Process", IEEE Trans. on Electron Devices, Vol. 35, No. 11, pages 1829-1833, November 1988; D. J. Sheldon, et al., "Application of a Two-Layer Planarization Process to VLSI Intermetal Dielectric and Trench Isolation Processes", IEEE Trans. on Semiconductor Manufacturing, Vol. 1, No. 4, pages 140-146, November 1988; and S. R. Wilson et al., "HIGH PERFORMANCE, FOUR METAL LAYER INTERCONNECT SYSTEM FOR BIPOLAR AND BIMOS CIRCUITS", IEEE VMIC Conf.(June 12-13, 1990), pages 42-47, 1990).
Now, the block resist process will be explained with reference to FIGS. 3A to 3D.
First, an oxide film 4 is formed on a patterned metal layer 3 by use of a plasma CVD process, as shown in FIG. 3A. Then, a resist film 5 is deposited, and the deposited resist film 5 is patterned in a known lithographic process as shown in FIG. 3B, by using a negative or inverted mask of the mask pattern for the interconnection metal layer 3. Furthermore, a second resist film 7 is deposited on the whole surface to completely planarize the resist surface, as shown in FIG. 3C. Thereafter, an etch-back is performed by an anisotropic etching under the condition that the selective etching ratio of the resist to the oxide film is 1:1, so that a planarized interlayer film 4 is formed as shown in FIG. 3D.
Here, a pattern width of the patterned first resist film has to be smaller than that of an inverted pattern of the patterned interconnection layer. Referring to FIG. 4, there is shown a graph illustrating a relation between the flatness property of the post-planarization interlayer film and the space between the patterned interconnection layer and the patterned first resist film.
If the patterned first resist overlaps the patterned interconnection layer, the second resist overlaps the first resist in the vicinity of the patterned interconnection layer, and therefore, a block resist is formed in the vicinity of the patterned interconnection layer, with the result that when the etch-back process is performed, the oxide film is protected in the vicinity of the patterned interconnection layer so that a step is formed in the vicinity of the patterned interconnection layer. On the other hand, if the space between the patterned interconnection layer and the patterned first resist is too wide, after the second resist is coated, concaves are generated on the second resist layer, with the result that, after the etch-back process is performed, concaves are also formed in the etched-back interlayer film. This is ordinarily called a "bat wing". In other words, the resist profile is copied to the etched-back interlayer film.
Accordingly, the patterned first resist is required to be smaller than the interconnection pattern by a margin corresponding to the thickness of the interlayer film.
Incidentally, as an example of avoiding the margin between the interconnection pattern and the patterned first resist, the above referred Japanese Patent Application Laid-open No. JP-A-60-245229 proposed to isotropically etch the oxide film.
Referring to FIGS. 5A to 5C, there are illustrated the interlayer film planarization based on the block resist process utilizing the isotropic etching.
As shown in FIG. 5A, after an interlayer oxide film 4 is formed, a patterned resist layer 5 is formed on the oxide film 4 by use of an inverted mask of the mask for forming a patterned interconnection layer 3. Then, an isotropic etching is performed using a hydrofluoric acid by removing the interlayer oxide film 4 by a thickness (for example, 0.8 .mu.m) which is smaller than the step difference, so that the steps on the interlayer oxide film 4 are removed as shown in FIG. 5B. Finally, the resist 5 is removed, so that the planarized interlayer film 4 is obtained as shown in FIG. 5C.
As seen from the above, the block resist process utilizing the anisotropic etching requires to prepare the inverted masks of the number corresponding to that of the interlayer films. In addition, since the margin between the mask for the patterned interconnection and its inverted mask depends upon the thickness of the interlayer film formed in the interlayer film formation process, a different mask is required for each interlayer film formation process. In this connection, since the mask for the patterned interconnection and its inverted mask for the first resist are used, a problem of misalignment inevitably occurs. Furthermore, since there is possibility that the block resist is not formed in the region of the margin between the mask for the patterned interconnection and its inverted mask for the first resist because of the restriction of the minimum size in the resist pattern, the flatness of the interlayer film is locally deteriorated.
In the block resist process utilizing the isotropic etching, on the other hand, another problem is encountered. Since the hydrofluoric acid widely used in the isotropic etching also etches aluminum of the interconnection conductor material, it is not possible to perform the isotropic etching a depth greater than the thickness of the oxide film. As a result, undulations is produced on the interlayer film, and therefore, when an upper level aluminum interconnection layer is patterned, the aluminum layer is not sufficiently removed due to variation in coverage of the upper level aluminum layer, so that a short-circuit is easy to occur between the patterned interconnections.